The number of chips you can cut from a single silicon wafer depends on two things: the size of the wafer and the size of each chip (called a “die”). A standard 300mm wafer, the industry workhorse, can yield anywhere from a few dozen large data center processors to over 1,000 small mobile chips. The math is straightforward, but real-world manufacturing losses reduce that number significantly.
Wafer Size Sets the Starting Point
Modern chip fabrication overwhelmingly uses 300mm (12-inch) wafers, which have a usable area of roughly 70,685 square millimeters. Older fabs still run 200mm (8-inch) wafers with about 31,416 square millimeters of area, commonly used for less advanced chips like power management ICs and automotive sensors. The larger the wafer, the more dies you can fit, which is why the industry moved to 300mm wafers in the early 2000s and is now developing 450mm wafers for even greater throughput.
Die Size Determines the Count
The single biggest variable is the die size of the chip being manufactured. A small microcontroller might have a die of just 10 to 20 square millimeters, while a high-end processor can be 400 to 800 square millimeters. The basic calculation is simple: divide the wafer’s usable area by the die area. But because wafers are round and dies are rectangular, you lose usable silicon around the edges. This “edge loss” means the actual count is always lower than pure division would suggest.
Here are some rough estimates on a standard 300mm wafer to give you a sense of scale:
- Small die (50 mm²): Around 1,200 gross dies. Think of a basic sensor or a small wireless chip.
- Mid-size die (100 mm²): Around 600 gross dies. Apple’s A19 Pro, for example, has a die size of about 98.6 mm², so a single wafer fits roughly this many.
- Large die (300 mm²): Around 200 gross dies. This range covers many desktop and laptop CPUs.
- Very large die (600+ mm²): Around 100 or fewer gross dies. High-end data center GPUs and AI accelerators fall here, with some exceeding 800 mm².
How to Estimate Gross Dies Per Wafer
The most common approximation divides the wafer area by the die area, then subtracts the unusable edge. A widely used formula is:
Gross dies ≈ (π × (wafer radius)²) / (die area) − (π × wafer diameter) / √(2 × die area)
The first term gives you the theoretical maximum. The second term accounts for the partial dies along the circular edge that can’t be used. For a 300mm wafer and a 100 mm² die, this formula gives roughly 600 to 640 gross dies, depending on how the rectangular grid aligns with the circle. Online die calculators from semiconductor analysis firms let you plug in exact dimensions, including the width and height of the die and a “scribe lane” allowance (the thin gaps between dies where the wafer gets cut), to get a more precise number.
Why Yield Reduces the Final Count
Gross dies per wafer is a theoretical number. Not every die on the wafer will actually work. Tiny defects in the silicon, dust particles, or imperfections in the photolithography process can render individual dies non-functional. The percentage of working dies is called the “yield,” and it is one of the most closely guarded figures in semiconductor manufacturing.
Yield depends heavily on defect density, which is measured as the average number of defects per square centimeter of silicon. Larger dies are hit harder by defects because each die has more area where something can go wrong. A fabrication process with a defect density of 0.1 per cm² might produce a yield above 95% for a 50 mm² die but only 80% for a 300 mm² die. For the largest chips, yields can drop to 50% or lower, especially early in a new manufacturing process before engineers have worked out the kinks.
The net dies per wafer, meaning the number of electrically functional chips, is the gross die count multiplied by the yield rate. If a wafer holds 600 gross dies and the yield is 85%, you get about 510 usable chips. If yield drops to 60% on a difficult process, that same wafer produces only 360.
Why This Matters for Chip Cost
A single 300mm wafer processed at an advanced node (like 3nm or 5nm) can cost $15,000 to $20,000 or more. When you divide that wafer cost by the number of good dies, you get the manufacturing cost per chip before packaging, testing, and profit margins. This is why die size and yield are so critical to chip pricing.
A small mobile chip with a 100 mm² die and 90% yield might cost $25 to $35 per die in wafer cost alone. A massive 800 mm² AI accelerator with 50% yield could cost $400 or more per die just for the silicon. Chipmakers carefully balance die size against performance targets for exactly this reason, and techniques like chiplet designs (splitting one large chip into several smaller dies connected together) have become popular partly because smaller individual dies achieve much higher yields.
Factors That Shift the Number
Several design and manufacturing choices affect how many good chips come off each wafer:
- Scribe lane width: The narrow channels between dies where a diamond saw or laser cuts the wafer apart. Typical scribe lanes are 50 to 100 micrometers wide. Narrower lanes save space and squeeze out a few extra dies.
- Die shape: Nearly all dies are rectangular, but the aspect ratio matters. A nearly square die packs more efficiently on a round wafer than a long, narrow rectangle.
- Edge exclusion zone: The outer 2 to 3 millimeters of a wafer are typically excluded from die placement because the silicon quality degrades near the edge.
- Process maturity: New manufacturing nodes start with lower yields that improve over months or years as engineers identify and eliminate defect sources. A mature process at a well-run fab can achieve yields above 95% for reasonably sized dies.
For a quick ballpark, dividing 70,000 (the approximate usable area in mm² of a 300mm wafer) by your chip’s die area gets you in the right neighborhood. Then knock 10% to 40% off for edge loss and yield, depending on die size and process maturity, and you have a realistic estimate of how many working chips a single wafer produces.